HBM Capacity Timeline: When Does Supply Catch Demand?

Last Updated: April 23, 2026  •  Author: Semiconductor Supply Chain Analysis  •  Type: Sector Report

Executive Summary

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1. Current State (Q1 2026)

1.1 Market Share (by HBM Revenue)

SK Hynix's share has come down from 62% in mid-2025 because Samsung finally passed NVIDIA's HBM3E 12-hi qualification (September 2025 after an 18-month delay) and Micron has expanded to four major customers. But SK Hynix remains dominant in absolute revenue terms.

1.2 Current HBM Production Rates (Estimated, Q1 2026)

Important note on wafer conversion: Each HBM stack requires multiple DRAM die. An 8-hi HBM3E stack uses 8 DRAM die + 1 logic/buffer die. A 12-hi stack uses 12 DRAM die + 1 buffer die. Because the die must be thinned (to ~30-40 microns), tested, and then stacked with TSVs (through-silicon vias), the effective DRAM bit capacity consumed per wafer is roughly 2.5-3x what a conventional DRAM wafer would produce. So 300K wafers/month allocated to HBM removes the equivalent of ~750-900K wafers/month of conventional DRAM bit supply.

1.3 Current HBM Pricing (Q1 2026)

For comparison, conventional DDR5 DRAM trades at roughly $2-3/GB. HBM commands a 5-7x premium per GB due to the stacking, TSV, and advanced packaging complexity.

1.4 Latest Earnings Snapshots

SK Hynix Q1 2026 (reported April 24, 2026):

• Record quarter. Revenue approximately KRW 20+ trillion (~$15B+)
• Operating margin reported at ~72% -- higher than NVIDIA and TSMC
• HBM revenue estimated at $7-8B for the quarter (annualized run rate ~$28-32B)
• Guidance: HBM sold out for all of 2026; demand visibility extending into 2027
• CEO statement: "We see no signs of demand moderation"

Samsung Q1 2026 (reported April 2026):

• Operating profit surged ~700-800% year-over-year for semiconductor division
• HBM revenue tripled from year-ago levels
• Catching up after finally securing NVIDIA HBM3E qualification in Q3 2025
• Sold out all 2026 HBM supply
• Aggressive push on HBM4 to leapfrog SK Hynix

Micron FQ2 2026 (reported March 18, 2026):

• Record quarterly revenue driven by data center / AI demand
• HBM revenue growing rapidly, on track for $2B+ quarterly run rate
• Qualified with 4 major GPU/ASIC clients (NVIDIA, AMD, and likely 2 hyperscaler ASIC programs)
• Targeting 24% HBM market share by end of calendar 2026

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2. Company-by-Company Expansion Plans

2.1 SK Hynix

Current Base:

• Main HBM production: Icheon (M15, M16 fabs) -- legacy fabs being converted/optimized
• Packaging: Icheon advanced packaging lines
• Technology: Leading in HBM3E; MR-MUF (Mass Reflow Molded Underfill) process gives SK Hynix a thermal and yield advantage

Expansion Plans:

Technology Roadmap:

• HBM3E 12-hi: In volume production now (36GB per stack). Primary product for B300/Blackwell Ultra.
• HBM4 8-hi: Sampling to customers in 2026. Expected mass production H2 2026 or Q1 2027.
• HBM4 12-hi: Expected 2027-2028. This is what goes into NVIDIA Rubin.
• HBM4E: Roadmap item for 2028+.

Key Insight: The $16B Yongin cluster is the single largest announced HBM capacity investment. But it does NOT produce meaningful volume until late 2027 at the earliest. The near-term supply increase for SK Hynix is incremental -- optimizing existing fabs and converting conventional DRAM lines. SK Hynix has said its 2025 capex was raised 30% YoY specifically because they have demand visibility for 2026 HBM, not speculative capacity. They are also trying to stabilize memory prices, per Chairman Chey's comments -- they do NOT want a price crash.

Capex Estimate: SK Hynix total 2025 capex was approximately $12-13B (KRW 16-17T), with 2026 expected to be higher. The Yongin cluster alone is $16B spread over multiple years.

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2.2 Samsung

Current Base:

• Main DRAM fabs: Pyeongtaek (P1, P2, P3 operational), Hwaseong (legacy)
• HBM production started ramping meaningfully after NVIDIA qualification in Q3 2025
• Technology: TCB (Thermal Compression Bonding) process -- lost ground to SK Hynix's MR-MUF but improving yields

The Samsung Catch-Up Story:

Samsung was the HBM laggard through most of 2024-2025. Their HBM3E chips failed NVIDIA's thermal and reliability tests repeatedly, leading to an 18-month qualification delay. They finally passed in September 2025 and began shipping to NVIDIA in Q3 2025. Since then, they have been in aggressive ramp mode and sold out their 2026 supply.

Expansion Plans:

Technology Roadmap:

• HBM3E 8-hi: In volume production (qualified by NVIDIA Q3 2025)
• HBM3E 12-hi: Cleared NVIDIA tests after 18-month setback (September 2025). In production ramp.
• HBM4 8-hi: Samsung is aggressively pushing to be first. Currently in final qualification phase. Claims readiness for mass production in H2 2026.
• HBM4 12-hi / 16-hi: 2027-2028 roadmap.

Key Insight: Samsung is the wildcard. They lost 1.5 years of HBM market share due to yield/qualification issues. Their 50% capacity increase in 2026 is the single largest year-over-year capacity jump among the three companies. If their HBM4 qualification succeeds before SK Hynix's, they could meaningfully close the market share gap. However, Samsung has a track record of over-promising on HBM timelines, so this deserves skepticism. The P4 fab pivot (from foundry-focused to hybrid memory) shows how aggressively they are chasing HBM.

Capex Estimate: Samsung's semiconductor capex for 2025 was approximately $35-40B total (memory + foundry), with 2026 expected at a similar or higher level. The memory/HBM portion is estimated at $15-20B.

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2.3 Micron

Current Base:

• Main DRAM fabs: Hiroshima, Japan (primary HBM production); Taichung, Taiwan; Boise, Idaho
• HBM packaging: Singapore (advanced packaging facility)
• Technology: Solid execution; first to ship HBM3E 8-hi to market initially, though SK Hynix quickly caught up

Expansion Plans:

Technology Roadmap:

• HBM3E 8-hi (24GB): In volume production, shipped to NVIDIA and others
• HBM3E 12-hi (36GB): In production ramp (mass production in 2025-2026)
• HBM4: Ships in 2026 (samples), mass production in 2027. Micron confirmed HBM4 readiness at its FQ2 2026 earnings.

Key Insight: Micron is the smallest of the three in HBM but growing the fastest in percentage terms. The $9.6B Hiroshima fab is a transformative investment -- it nearly doubles Micron's advanced DRAM capacity in Japan. However, like Yongin for SK Hynix, this does not produce meaningful volume until 2027. Micron's near-term HBM growth comes from converting existing lines and expanding Singapore packaging. Micron's advantage is its strong relationship with multiple customers (4 qualified clients, diversifying beyond just NVIDIA) and its 1-beta node leadership which gives it a die-size advantage.

Capex Estimate: Micron FY2026 capex guided at approximately $14-16B total.

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3. Total Industry Supply Forecast

3.1 HBM Supply by Company (Revenue, $B)

3.2 HBM Supply by Capacity (Estimated Total Industry Bit Production)

3.3 HBM Demand by Customer Segment

Critical note on ASIC demand growth: TrendForce reported in July 2025 that HBM demand from custom ASICs (Google TPU, Amazon Trainium, etc.) is expected to surge 80% in 2026. This is the demand vector most analysts underestimate. Every hyperscaler is designing their own AI chips, and every one of them needs HBM. This is additive to the GPU demand, not substitutional.

3.4 Supply vs. Demand Balance

When does supply catch demand? Based on current trajectories:

• Best case (for suppliers): Supply remains structurally tight through 2028, as SK Hynix's Chairman suggested at GTC 2026. This scenario requires ASIC demand to continue surging and HBM4 to create new pricing tiers.
• Base case: Supply roughly matches demand in H2 2027 / H1 2028. Pricing pressure begins but is modest (5-15% ASP declines) because the mix shifts to higher-value HBM4.
• Bear case: If AI capex growth decelerates (spending cuts, regulation, recession), supply could exceed demand by mid-2027, leading to meaningful price cuts. This is the TrendForce warning from July 2025 about "double-digit drop risks."

The key insight: Even in the base case, HBM "oversupply" looks very different from conventional DRAM oversupply. HBM has long-term contracts (12-18 month agreements), limited number of customers (NVIDIA alone is probably 50%+ of demand), and a technology upgrade cycle (HBM3E to HBM4) that resets pricing. This is NOT the commodity DRAM market.

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4. The Conventional DRAM Supply Squeeze

4.1 The Wafer Diversion Math

This is one of the most under-appreciated dynamics in the memory industry.

As of 2026, HBM consumes approximately 22-25% of total industry DRAM wafer starts. But here is the critical math:

• An HBM3E 12-hi stack requires 12 DRAM die + 1 buffer die = 13 good die per stack
• Each die must be thinned to ~30-40 microns (vs. ~700-750 microns for standard DRAM)
• The thinning, TSV formation, and stacking process has yield losses at each step
• Net result: 1 HBM wafer produces approximately 1/3 the DRAM bit output of a conventional DRAM wafer

So when the industry allocates 25% of wafer starts to HBM, the effective conventional DRAM bit supply reduction is much larger:

• 25% of wafers go to HBM
• But those wafers produce only 1/3 the bits per wafer
• Effective bit supply from those wafers: 25% / 3 = ~8% of total bit supply
• Lost conventional DRAM bit supply: 25% - 8% = ~17% of total industry DRAM bits are "lost" to HBM production

4.2 Impact on Conventional DRAM

This is already playing out in 2026. Reports indicate DDR5 prices are rising due to wafer diversion. The memory chip shortage of 2026 is being driven not by a demand surge for PCs/phones but by the supply-side effect of HBM eating wafer capacity.

4.3 The Self-Hedging Dynamic

This is why the memory cycle is different this time:

• Scenario A: HBM demand stays strong -- Memory companies print money on HBM at 50-70% margins. Conventional DRAM stays tight because wafers keep getting diverted. Win-win.
• Scenario B: HBM demand softens -- Companies can convert some HBM wafer capacity back to conventional DRAM. This relieves the conventional DRAM shortage but also floors HBM supply growth, preventing a true HBM glut.
• Scenario C: Both stay strong -- The best scenario. This is what is actually happening as of Q1 2026.

The conventional DRAM squeeze is a natural hedge against HBM oversupply risk. The memory companies (especially SK Hynix) are explicitly aware of this and are managing the transition carefully. SK Group Chairman Chey's statement about "trying to stabilize memory prices" is a direct reference to this dynamic -- they are NOT going to flood the market with HBM capacity at the expense of cratering conventional DRAM.

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5. Bottlenecks

5.1 TSMC CoWoS Packaging (THE Primary Bottleneck)

HBM stacks are useless without advanced packaging. Every AI GPU needs its HBM stacks integrated onto a substrate alongside the GPU die using TSMC's CoWoS (Chip-on-Wafer-on-Substrate) or similar advanced packaging technology.

Current Status (Q1 2026):

• TSMC has been capacity-constrained on CoWoS since 2023
• They have been aggressively expanding: building new packaging lines at Longtan (Taiwan), AP6/AP7 fabs
• TSMC raised its CoWoS capacity targets for 2026-2027 across the board
• Despite expansion, demand continues to outpace capacity -- TSMC is now outsourcing some CoWoS packaging to ASE, Amkor, and others
• Estimated CoWoS capacity in 2026: ~35,000-45,000 wafers/month (up from ~15,000-20,000 in 2024)

Expansion Timeline:

Key insight: CoWoS is the pacing bottleneck, NOT HBM DRAM production. Even if Samsung, SK Hynix, and Micron can produce more HBM stacks, those stacks sit in inventory if TSMC cannot package them onto GPU substrates. This is why TSMC is outsourcing packaging for the first time -- a historic move that shows just how dire the constraint is.

5.2 HBM Stacking / Advanced Packaging at Memory Companies

The memory companies themselves have their own packaging bottleneck:

SK Hynix: MR-MUF (Mass Reflow Molded Underfill)

• SK Hynix's proprietary process that gives them a yield and thermal advantage
• They have been expanding MR-MUF capacity aggressively
• MR-MUF is the key reason SK Hynix has maintained 50%+ market share
• Expansion is ongoing but MR-MUF lines are expensive and complex

Samsung: TCB (Thermal Compression Bonding)

• Samsung's traditional process; lower throughput than MR-MUF
• Samsung has been improving TCB yields and is also developing hybrid bonding for HBM4
• TCB yield issues were a primary reason for Samsung's 18-month NVIDIA qualification delay
• Samsung is now achieving acceptable yields but still trails SK Hynix

Hybrid Bonding (HBM4 and Beyond)

• HBM4 will transition from traditional micro-bump connections to hybrid bonding (copper-to-copper direct bonding)
• Hybrid bonding enables finer pitch, higher bandwidth, and better thermals
• But it is a new process with its own yield challenges
• All three companies are investing heavily in hybrid bonding R&D
• This transition creates a potential yield "reset" where first-mover advantage matters enormously

5.3 Yield Challenges: 12-Hi and Beyond

The yield math matters enormously for supply: If HBM3E 12-hi yields are 65%, that means 35% of all stacking attempts produce defective stacks. This is 35% of capacity that is wasted. A 10-percentage-point improvement in yield (65% to 75%) is equivalent to ~15% more supply from the same installed capacity. Yield improvement is the single fastest way to increase HBM supply without building new fabs.

5.4 Which Bottleneck Breaks First?

Ranking of bottlenecks (most severe to least severe, as of Q1 2026):

1. TSMC CoWoS -- Still the #1 constraint. Being addressed aggressively but demand continues to outgrow supply. Outsourcing is a partial solution. Expected to ease meaningfully by H2 2027.
2. HBM stacking/packaging at memory companies -- #2 constraint. MR-MUF/TCB capacity is being expanded but requires specialized equipment with long lead times. Expected to ease by mid-2027.
3. DRAM wafer capacity -- Becoming tighter as HBM takes more share. New fabs (Yongin, Hiroshima new fab) don't produce until 2027-2028. This one actually gets WORSE before it gets better.
4. HBM4 yield immaturity -- Will become the dominant bottleneck in 2027 as the industry transitions from HBM3E to HBM4. Early HBM4 yields will be low, constraining supply even as raw wafer capacity increases.

Net assessment: The bottleneck sequence is: CoWoS (2024-2026) --> HBM packaging/yield (2026-2027) --> Wafer capacity (2027-2028). At no point in the next 2 years does every bottleneck ease simultaneously. This is why structural shortage persists.

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6. Investment Implications

6.1 Timeline for HBM Pricing Pressure

When to worry: The earliest investors should begin monitoring for HBM pricing pressure is Q3-Q4 2027. The trigger would be: (a) memory companies reporting HBM inventory build, (b) contract prices declining quarter-over-quarter, (c) AI capex growth decelerating (watch hyperscaler capex guidance).

6.2 Which Company Benefits Most?

Near-term (2026): SK Hynix

• 72% operating margins are extraordinary
• Dominant share + sold-out capacity = maximum pricing power
• MR-MUF advantage sustains through HBM3E lifecycle
• Risk: Share loss to Samsung/Micron is inevitable but manageable

Medium-term (2027): Samsung has the most upside optionality

• Coming from behind with 25-28% share and a 50% capacity increase
• If HBM4 qualification succeeds first, Samsung could gain 5-10 points of share
• P4 fab ramp adds significant capacity
• Samsung trades at a discount to SK Hynix on a P/E basis due to its HBM stumbles -- any catch-up story gets re-rated
• Risk: Samsung has a pattern of overpromising on HBM timelines. Their HBM4 claims deserve skepticism until NVIDIA qualification is confirmed.

Steady gainer: Micron

• Growing from 18-20% to 24%+ share
• $9.6B Hiroshima fab is a generational investment
• Strong process node (1-beta) gives die size advantage
• CHIPS Act subsidies reduce effective capex burden
• Most diversified customer base (4 qualified clients)
• Risk: Smallest player, least pricing power in a downturn

6.3 Key Triggers to Watch

Bullish triggers (extend the supercycle):

1. NVIDIA Rubin (R100) shipments pull forward -- each Rubin GPU uses HBM4, creating new demand
2. Hyperscaler ASIC demand continues surging 80%+ annually
3. HBM4 yields come in lower than expected -- constraining supply even as wafer capacity ramps
4. Sovereign AI programs (Middle East, Asia) create new demand pools
5. SK Hynix/Samsung signal continued supply discipline (not racing to crash prices)

Bearish triggers (signal the cycle is turning):

1. Memory companies report HBM inventory build (not sold out)
2. NVIDIA GPU shipment delays or order cancellations
3. Hyperscaler capex guidance cuts (watch Google, Microsoft, Amazon, Meta quarterly earnings)
4. HBM contract prices decline >10% QoQ
5. Samsung or Micron begin aggressive pricing to gain share (rational oligopoly breaks down)
6. CoWoS bottleneck resolves faster than expected (TSMC outsourcing succeeds at scale)

The single most important leading indicator: Listen to SK Hynix earnings calls for any change in the language around "sold out." As long as they say HBM capacity is "sold out" for the next 12+ months, the cycle is intact. The moment they say something like "we have good visibility" instead of "sold out," pricing pressure is approaching.

6.4 The Non-Consensus View

Most analysts are focused on "when does HBM supply catch demand" as a linear projection. Here is why that framing may be wrong:

1. HBM4 resets the clock. Every technology transition (HBM3E --> HBM4 --> HBM4E) requires re-qualification, new packaging, and endures early yield losses. This is NOT like commoditized DRAM where bit supply scales smoothly. Each new generation creates a temporary supply disruption.
2. The demand curve is exponential, not linear. AI training compute is growing 4-5x annually. Inference is growing even faster as models deploy. Every new AI model (GPT-5, Gemini Ultra, Claude 5) is larger and requires more memory. Demand forecasts based on current model sizes will underestimate future demand.
3. SK Hynix's Chairman saying "wafer shortage until 2030" is not just talking his book. He is the person with the best demand visibility in the industry (direct line to NVIDIA's order book). If NVIDIA's internal GPU shipment plans for 2028-2030 require more HBM than the industry can produce, then the shortage truly could persist.
4. The conventional DRAM squeeze creates a price floor. Even if HBM-specific ASPs decline, the overall memory industry revenue is supported by rising conventional DRAM prices. This prevents the profit collapse that normally characterizes memory downturns.

6.5 Summary: Position Sizing Guidance

Given the AGI premise: memory demand only goes up. Recursive self-improvement means ever-larger models, ever-more inference, ever-more GPUs, ever-more HBM. The memory companies are building capacity for a world where AI compute demand grows 10x in 5 years. If anything, they are UNDER-building. The risk is not a demand shortfall -- it is that they cannot build capacity fast enough.

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Appendix: Key Data Points by Source

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This analysis reflects data available as of April 23, 2026. The HBM market is evolving rapidly. Key earnings to watch: SK Hynix (quarterly), Samsung (quarterly), Micron (quarterly on different fiscal calendar), NVIDIA (for demand signals), and hyperscaler capex disclosures (Google, Microsoft, Amazon, Meta).